1. Field of the Invention
The present invention relates to a resampling method and a resampler circuit for use in a digital filter, particularly in a so-called interpolation filter, which is installed in a digital decoder or the like and capable of effectuating a timing recovery function.
2. Description of the Related Art
In accordance with the remarkable development in the field of semiconductor technique, conventional analog signal processing employing analog electronic circuit elements such as resistors, capacitors, coils, OP amplifiers and so on is gradually shifting to signal processing in a digital fashion which is the so called digital signal processing, in various fields including the field of communications, audio and/or visual field, as well as the fields of measurement, control and so on.
It is required to transmit digital data or discrete data between systems in which the digital signal processing is essential. However, in a case that digital data is transmitted (for communication), it is normally transmitted to a remote place in terms of distance or time, and due to this, the data transmission side and the data reception side cannot share the same time, whatever the medium for the data transmission is.
FIG. 7 shows an exemplary view for explaining the relationship between transmitted data and a received waveform in a digital transmission system, although it is applicable to many fields other than the field where this digital transmission system is employed.
As shown in the figure, the discrete digital data is transmitted from a transmission side to a reception side at predetermined time intervals. Digital data transmitted by way of a transmission line (such as a cable, a telephone line, wireless communication line and so on) between the transmission side and the reception side is deteriorated during transmission due to the transmission line characteristics, so that the original shape of the digital data is somewhat transformed before it is finally received as an analog waveform data at the reception side. This received data normally contains some noise due to interference possibly caused during data transmission.
A digital signal processing device at the reception side requires a function to recover the data of an analog waveform to the original digital data transmitted from the transmission side, and this recovering process is called a data recovery. On the other hand, in an analog signal processing system, there is no occurrence of data drop or the like from an analog waveform, as the received data of analog waveform can be processed just as it is.
However, in the digital signal processing system, since it is necessary to perform sampling of digital data from the received analog waveform, the data which has not been sampled is regarded as being lost. Therefore, in order to correctly recover the received data at the reception side, the transmission side has to send digital data in accordance with a predetermined protocol.
In short, transmission of digital data from the transmission side to the reception side is equivalent to a transmission of square pulses. Although the square pulse requires a wide-band transmission line as it has a wide frequency spectrum characteristic, the transmission line used for this purpose has to be limited to the frequency band in which the data can be correctly transmitted, as there is a limitation in the frequency resources.
FIG. 8 is an exemplary view showing the transformation of digital data when it is transmitted by way of a low pass filter. For example, when the wide frequency band component of digital data is eliminated by use of a low pass filter, the waveform of the square pulse is transformed to a gentle taper-like waveform as shown in the right-side portion of FIG. 8, resulting thereby in an expansion of the pulse width. In a case that digital data is transmitted by use of a T-width square pulse train, the pulse width is expanded due to the limitation of band width, and as a result, the adjacent pulses are superimposed with each other, causing thereby an interference (intersymbol interference) between the transmission waveforms. In a case that a digital data which is pulse information is transmitted at time intervals of T, if there is no such superimposition of adjacent transmission waves at sampling points T, correct pulse information can be taken out at the reception side even if a distortion has occurred in the transmission waveform.
The Nyquist""s first standard is widely known as a condition under which a band limitation is made possible even without generating an intersymbol interference. According to this Nyquist""s first standard, the required minimum frequency band that does not cause any intersymbol interference at sampling points of every time interval T is T/2.
FIG. 9 is an exemplary view of a filter characteristic that does not cause the intersymbol interference. In the figure, when a pulse signal is input at timing intervals of T by use of an ideal low pass filter through which only the signal within the frequency band between the frequency f=0 and the frequency f=1/2T (hereinafter referred to just as Nyquist frequency) is allowed to pass, or by use of a low pass filter having an odd-symmetrical transmission characteristic about the Nyquist frequency 1/2T, then a response, namely an impulse response (refer to FIG. 2) becomes amplitude zero at the time point t=xc2x1nT, so that even when impulse responses are superimposed with each other, there will be no intersymbol interference generated as long as the data sampling is performed at t=xc2x1nT.
There is a roll-off filter as a practical filter that satisfies the Nyquist""s first standard. The characteristic of this roll-off filter is a characteristic shown in FIG. 9, and its impulse response is shown as a waveform 1 that can be obtained by the SINC function shown in FIG. 2. However, even when a digital data is transmitted from the transmission side in a state that there is no intersymbol interference as shown above, the data transmission interval T from the transmission side and the sampling interval T of the thus transmitted data at the reception side are not always the same. Generally, in a digital signal processing system, this data sampling interval is generated by a crystal oscillator. However, even if the same crystal oscillator is used at the transmission side and the data reception side, the operation thereof will not be exactly the same.
For example, in a case that there is caused an error of 1 ppm between the crystal oscillator at the transmission side and that at the reception side, if the system is operating at 10 MHz or so, 10 data at every one second can be lagged therebetween. Further, even if the frequency at the both sides are exactly the same, if there is a time lag between the transmitting interval T at the data transmission side and the sampling point at the data reception side, there will be no way to obtain the correct data forever. Further, in the digital transmission system, there is a problem that the sampling points cannot be transmitted from the data transmission side to the data reception side.
Considering the above, the data reception side needs to recover the frequency of the transmission side (data transmission interval) and the sampling point from the received data. The processing operated at the reception side is called a timing recovery, and a block that implements this processing is called a timing recovery circuit.
Conventionally, it has been common to implement this timing recovery circuit by combination of digital processing and analog processing. However, in recent days, there are many types of timing recovery circuits that perform all the operations by use of digital processing only, and this kind of circuit is called a digital timing recovery circuit, or a resampler circuit.
The operation of the conventional digital timing recovery circuit or resampler circuit is now explained below.
FIG. 10 is an exemplary view showing the method of calculating interpolation data.
The conventional resampler circuit has only to calculate an arbitrary timing by interpolating a sampled signal, so that it can be implemented by a low pass filter (FIRxe2x80x94Finite Impulse Response) having a variable coefficient and a limited number of taps. The principle of resampling is shown by the following formula (1)                               y          ⁡                      (            t            )                          =                              ∑                          n              =                              -                ∞                                      ∞                    ⁢                      xe2x80x83                    ⁢                                                    x                ⁡                                  (                  nT                  )                                            ·              SINC                        ⁢                          {                                                (                                      t                    -                    nT                                    )                                /                T                            }                                                          (        1        )            
Here, X(nT) represses a sampled signal, SINC( ) represents a SINC function, T represents a sampling interval, and y(t) represents an original analog signal of the sampled signal x(nT) (received waveform).
The above formula (1) is an expression for performing adding operation of the waveform values shown in FIG. 10, and in a case that the time point is T, the value of y(T) will be obtained by the following formula (2).
y(T)= . . . +x(T)xc2x7SINC(0)+x(2T)xc2x7SINC(xe2x88x921)+x(3T)xc2x7SINC(xe2x88x922)+ . . . xe2x80x83xe2x80x83(2)
FIGS. 11A and 11B are exemplary views showing a method of calculating the interpolation data in the resampler circuit.
FIG. 11A shows a resampler circuit having a configuration of the FIR filter with the value n in the formula (1) being specified. Here, SINC(0), SINC(xe2x88x921), SINC(xe2x88x922) . . . are coefficients each corresponding to the input value x(nT), and y(T) is a total value to be output resulting from multiplication of each of the coefficients corresponding to each input value x(nT) in the case of n being 0, 1, 2, 3 . . .
Next, in a case of the time point T+txe2x80x2 which has passed for a predetermined time period txe2x80x2 from the time point T, the value of y(T+txe2x80x2) will be as shown by the following formula (3)
y(T+txe2x80x2)= . . . +x(T)xc2x7SINC(txe2x80x2)+x(2T)xc2x7SINC(xe2x88x921+txe2x80x2/T)+x(3T)xc2x7SINC(xe2x88x922+txe2x80x2/T)+ . . . xe2x80x83xe2x80x83(3)
When the above formula (3) is implemented in the FIR filter, it becomes a resampler circuit having a configuration of FIG. 11B. In FIG. 11B, although the value of input x(nT) is same as the case for obtaining the value y(T), the coefficients become SINC(txe2x80x2/T), SINC(xe2x88x921+txe2x80x2/T), SINC(xe2x88x922+txe2x80x2/T) . . . , and thus this circuit employs coefficients at the time points which have been shifted for the time period txe2x80x2 from the case of y(T) shown in FIG. 11A.
Accordingly, even when the sampling point is defined at timing intervals of T, with the provision of coefficients of the SINC function between the sampling points, an arbitrary value which has not really been sampled between the sampling time points can be calculated. This SYNC function is nothing but an impulse response with respect to the reference pulse (scale 1). After all, the resampler circuit can perform the timing recovery by calculating the digital data which has not been sampled, but even without changing the sampling points by use of the above technique.
In the resampler circuit as explained above, let us consider the case of the coefficients indicated by a SINC function shown in FIG. 2, as to the data processing by the resampler circuit at an arbitrary time point T+txe2x80x2 with the value for n being 10. In FIG. 2, the waveform 1 denotes a SINC function, namely a coefficient by which the data to be sampled is multiplied. The lateral axis denotes a time axis, which expresses the lapse of time from the right toward the left.
In the waveform 1 shown in FIG. 2, if the time point at which the coefficient becomes maximum is zero (hereinafter referred to just as a reference time 0), then the value at the reference time 0 is a maximum value 1 (center tap). Further, the coefficient shown by this SINC function has a value symmetrical to both lateral sides about the time point 0. In either direction from the time point 0 is toward positive or negative (rightward or leftward), the coefficient of the time which is away for absolute time period T therefrom is always 0, and in this case, there is no intersymbol interference. There exists a timing point txe2x80x2 at which the received data is actually sampled within the time interval T. If the sampling period T is an integer value, then txe2x80x2 is a value below a decimal point.
With the condition that the data sampled at time intervals of T are Zxe2x88x920, Zxe2x88x921, Zxe2x88x922, Zxe2x88x923, Zxe2x88x924, Zxe2x88x925, Zxe2x88x926, Zxe2x88x927, Zxe2x88x928, Zxe2x88x929 in the reverse order of time lapse (from left to right in the figure) since the delayed time amount for obtaining the coefficient for the formula for calculating the sampled data is txe2x80x2, the coefficients employed for forming the data to be interpolated will be, as shown in FIG. 2, e, d, c, b, a, axe2x80x2, b, bxe2x80x2, cxe2x80x2 dxe2x80x2 and exe2x80x2 in the reverse order of time lapse. Due to this, the digital data to be interpolated will be obtained by the following formula (4):
(Z0xc2x7e)+(Zxe2x88x921xc2x7d)+(Zxe2x88x922xc2x7c)+(Zxe2x88x923xc2x7b)+(Zxe2x88x924xc2x7a)+(Zxe2x88x925xc2x7axe2x80x2)+(Zxe2x88x926xc2x7bxe2x80x2)+(Zxe2x88x927xc2x7cxe2x80x2)+(Zxe2x88x928xc2x7dxe2x80x2)+(Zxe2x88x929xc2x7exe2x80x2)xe2x80x83xe2x80x83(4)
Since the conventional resampler circuit is configured as above, it is necessary to operate 10 times of multiplication and 9 times of addition in order to obtain the digital data to be interpolated in the formula (4). In other words, it requires a lot of time to perform arithmetic processing such as multiplication and addition. If such multiplication and addition are executed in parallel in order to reduce the time to be required for execution of the arithmetic operation, then 10 multipliers, 10 coefficient ROMs and 9 adders are required. For this reason, in this case above, there arises a problem that the scale of the hardware becomes too large.
FIG. 12 is an exemplary view showing a conventional resampler circuit, namely a FIR filter which is the circuit for executing the formula (4). In the figure, FF-x, namely FF-0 to FF-99 are registers, each of which is a circuit for storing the sampled data having arbitrary number of bits. When the clock signal CLK is fed to each of the registers FF-x, each one inputs the data in synchronization with the rising or falling edge of the clock signal, retains the thus obtained input data therein, and outputs the data to the next register one after another. Variation of the clock signal CLK indicates the sampling interval of the digital data, that is, the time interval T.
The registers FF-x, namely FF-1 to FF-9 are connected in series, and transmit the sampled data in accordance with the variation of level of the clocksignal CLK from FF-0 to FF-9 in order. The digital data output from the FF-0 is Z0, the digital data output from the FF-1 is Zxe2x88x921, and the digital data output from the FF-9 is Zxe2x88x929. That is, the data of the latest time point is Z0, and that of the oldest time point is Zxe2x88x929.
In FIG. 12, ADDx, namely ADD0 to ADD9 are adders, each of which has function of adding two input digital data, and outputs the thus added result. MPYX, namely MPY1 to MPY9 are multipliers, each of which has a function of multiplying two input digital data with each other, and outputs the thus multiplied result.
ROMx, namely ROM0 to ROM9 are circuits, each of which stores coefficient data of the SINC function. Here, ROM denotes a Read Only Memory (memory that is only for reading out the data therefrom), and is a circuit that externally outputs the data stored in the storage area corresponding to the value input from outside (which is called an address data). Each of the ROMx (x=0xcx9c9) is a circuit that inputs the discrepancy txe2x80x2 of the sampling interval as an address and outputs a coefficient value corresponding to the input address data, that is, a function value obtained from the SINC function shown in FIG. 2.
If the time interval between one arbitrary data sampling time T and the next data sampling time T+1 is divided into 128 time points, the discrete digital data are stored as the coefficient values in the storage area within the ROM indicated by the address that corresponds to each of the thus divided 128 time points. In FIG. 12, IN denotes an input digital data to be sampled, and OUT denotes an output digital data to which a timing recovery has already been applied.
As explained heretofore, the conventional resampler circuit requires many arithmetic operations such as multiplication and the like, making thus its processing time long, whereby the hardware scale becomes large as a whole.
The present invention has been proposed to solve the problems aforementioned, and it is an object of the present invention to provide a method of resampling or a resampler circuit that can be implemented by a relatively small-scale hardware capable of reducing the number of arithmetic operations such as multiplication, the number of multipliers and ROM, and also capable of minimizing the scale of the ROM used and so on.
In order to achieve the above object, the method of resampling according to the first aspect of the present invention comprises the steps of: in a state that a plurality of registers storing input data of time series obtained through sampling operation are divided into a former half group and a latter half group, and positioned in such a manner that the first one of the former group and the last one of the latter group are paired with each other, adding the input data stored in each of the paired registers except the first one of the former group and the last one of the latter group by use of a plurality of first adding means, multiplying the data output from the first register of the latter half group in the plurality of registers by the coefficients obtained from a first storage means storing the coefficients obtained by a SINC function during the time period between a reference time corresponding to a center tap of the SINC function and a first time point which is after a lapse of sampling interval T by use of a first multiplying means, multiplying the data output from the last register of the former half group within the plurality of registers by the coefficients obtained from a second storage means storing the coefficients obtained by the SINC function during the time period between the reference time and a second time point after a lapse of sampling interval xe2x88x92T by use of a second multiplying means, adding the data output from each of the plurality of first adding means and the coefficients obtained from each of a plurality of third storage means storing the coefficients obtained by the SINC function at time intervals xe2x88x92T from the second time point by use of a plurality of third multiplying means each corresponding to each of the plurality of third storage means, adding the data output from the first multiplying means and the data output from the second multiplying means by use of a second adding means, and sequentially adding the result of addition output from the second adding means and the output from each of the plurality of third multiplying means, so as to output thereafter, by use of a plurality of third adding means.
The resampler circuit according to the second aspect of the present invention is constructed such that it comprises: a plurality of registers connected in series, each of which stores, synchronizing with the clock signals, input data of time series obtained through sampling operation, and sequentially outputs the input data to the following stage, a plurality of adding means for adding input data stored in each of a plurality of paired registers, which paired registers being provided by dividing a plurality of registers into a former half and a latter half group, and positioned in such a manner that the first one of the former half group and the last one of the latter half group are paired with each other, and each of the plurality of adding means being provided as corresponding to each of the pair of registers, except the first one of the former half group and the last one of the latter half group, a first storage means for storing coefficients obtained by a SINC function during the time period between the reference time corresponding to a center tap of the SINC function and a first time point which is after a time lapse of sampling interval xe2x88x92T, a second storage means for storing coefficients obtained by the SINC function during the time period between the reference time and second time point which is after a time lapse of sampling interval xe2x88x92T, a plurality of third storage means for storing coefficients obtained by the SINC function at the sampling intervals xe2x88x92T counting from the second time point, a first multiplying means for multiplying the data output from the first register of the latter half group in the plurality of registers by the coefficients obtained from the first storage means, a second multiplying means for multiplying the data output from the last register of the former half group in the plurality of registers by the coefficients obtained from the second storage means, a plurality of third multiplying means for multiplying the data output from each of the plurality of first adding means by the coefficients obtained form each of the plurality of third storage means corresponding to each of the plurality of first adding means, a second adding means for adding the data output from the first multiplying means by the data output from the second multiplying means, and a plurality of third adding means for sequentially adding the result of addition output from the second adding means and the output data from each of the plurality of third multiplying means, and outputting thereafter, each of which third adding means corresponding to each of the third multiplying means and connected in series.
The resampler circuit according to the third aspect of the present invention is constructed in such a manner that it comprises: a plurality of registers connected in series, each of which stores, synchronizing with the clock signals, input data of time series obtained through sampling operation, and sequentially outputs the input data to the following stage, a first storage means for storing coefficients obtained by a SINC function during the time period between the reference time corresponding to a center tap of the SINC function and a first time point which is after a time lapse of sampling interval xe2x88x92T, a second storage means for storing coefficients obtained by the SINC function during the time period between the reference time and second time point which is after a time lapse of the sampling interval xe2x88x92T, a plurality of fourth storage means for storing the coefficients obtained by the SINC function corresponding to a half of the time width of each of the sampling intervals T counting from the first time point and the coefficients obtained by the SINC function corresponding to a half of the time width of each of sampling intervals xe2x88x92T counting from the second time point, a first multiplying means for multiplying the data output from the last register of a former half group of the two groups obtained by dividing the plurality of registers mutually connected in series by the coefficients obtained from the first storage means, a second multiplying means for multiplying the data output from the first register of a latter half group of the two groups by the coefficients obtained from the second storage means, a plurality of fourth multiplying means for multiplying the coefficients obtained from each of the plurality of fourth storage means by the data output from each of the plurality of registers corresponding to each of the fourth storage means, and a plurality of adding means connected in series for sequentially adding up the data from each of the fourth multiplying means, the first multiplying means and the second multiplying means.
The resampler circuit according to the fourth aspect of the present invention is constructed in such a manner that it comprises a plurality of registers connected in series, each of which stores, synchronizing with the clock signals, input data of time series obtained through sampling operation, and sequentially outputs the input data to the following stage, a plurality of adding means for adding input data stored in each of a plurality of paired registers, the paired registers being provided by dividing a plurality of registers into a former half and a latter half group, and positioned in such a manner that the first one of the former half group and the last one of the latter half group are paired with each other, and each of the plurality of adding means being provided as corresponding to each of the pair of registers, except the first one of the former half group and the last one of the latter half group, a first storage means for storing coefficients obtained by a SINC function during the time period between the reference time corresponding to a center tap of the SINC function and a first time point which is after a time lapse of sampling interval T, a second storage means for storing the coefficients obtained by the SINC function during the time period between the reference time and second time point which is after a time lapse of sampling interval xe2x88x92T, a plurality of fourth storage means for storing the coefficients obtained by the SINC function corresponding to a half of the time width of each of the sampling intervals xe2x88x92T starting from the second time point, a first multiplying means for multiplying the data output from the first register of the latter half group in the plurality of registers by the coefficients obtained from the first storage means, a second multiplying means for multiplying the data output from the last register of the former half group in the plurality of registers by the coefficients obtained from the second storage means, a plurality of third multiplying means for multiplying the data output from each of the plurality of first adding means by the coefficients obtained form each of the plurality of fourth storage means corresponding to each of the plurality of first adding means, a second adding means for adding the data output from the first multiplying means by the data output from the second multiplying means, and a plurality of third adding means for sequentially adding the result of addition output from the second adding means and the output data from each of the plurality of third multiplying means and outputting thereafter, each of the third adding means corresponding to each of the third multiplying means and connected in series.
The resampler circuit according to another aspect of the present invention is constructed in such a manner that each of the plurality of fourth storage means is provided with an inverting means for inverting the input address data indicating a specific storage area storing the coefficients, and a selecting means for selecting either the output from the inverting means or the input address data, and outputs the coefficient from the storage area connected to word lines corresponding to the number of bits of the address data output from the selecting means.
The resampler circuit according to another aspect of the present invention is constructed in such a manner that one part of the plurality of fourth storage means takes in the input address data by way of address lines corresponding to the upper nxe2x88x921 bits (wherein n denotes the total number of bits) of the input address data, and output the coefficient stored in said storage area on the basis of said input address data.